1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a dynamic semiconductor memory comprising a control circuit with which cell data is not destroyed by a malfunction.
2. Description of the Related Art
With advances in the integration circuit technique, semiconductor memory devices, and particularly dynamic random access memories (DRAMs; to be referred to as DRAMs hereinafter) have been widely used in the field of electronics. Large-capacity DRAMs are used in a field requiring a very large memory capacity, e.g., the field of image memories. In this field, stored data must be sequentially read out at high speed.
Operation modes such as a fast page mode and an extended data output mode (EDO) are devised and used in correspondence with this high-speed read system.
FIG. 1 shows the basic arrangement of a DRAM of this high-speed read system. As for the flow of signals, a column address input and a row address input are time-divisionally input to and latched by a column address buffer 1 and a row address buffer 2 in synchronization with selection signals (not shown). A row decoder 3 selectively drives a word line to access the row of a desired memory cell in a memory cell array 10.
Information in the memory cell on the accessed row is transferred to a bit line (not shown) and amplified by a sense amplifier 8. At the same time, information is rewritten in this memory cell.
A column decoder 4 selectively drives a selection gate 7 in accordance with the column address input and selects an output from the sense amplifier 8 corresponding to a desired column. This selected information is read out to a data line (not shown) and transferred to an I/O buffer 9 through a data buffer 6. The I/O buffer 9 is connected to an I/O portion (not shown).
Upon a change in the column address input signal, an address transition detector 5 generates a data line equalization signal and sends a sense signal to the data buffer 6.
To prevent destruction of memory cell information, the series of operations are controlled in accordance with an internal synchronization signal and executed in a predetermined order at predetermined timings.
In such a DRAM, noise generation in the column address buffer 1 greatly increases the possibility of causing a malfunction. Assume that the column decoder 4 selects a column different from the currently selected column due to the noise. In the address transition detector 5, however, noise generally tends to be suppressed due to the internal characteristics of this circuit, so that an output from the address transition detector 5 is not switched with the noise. For this reason, no equalization operation for a data line or data sense operation is performed. Therefore, the data on this data line may flow into the newly switched column (bit line) to destroy data.